ZUSBOPTSC01ZAC datasheet(99/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

PWM 0–2 Duty Cycle High and Low Byte

Z8FMC16100 Series Flash MCU

Product Specification

PWMRH and PWMRL—PWM Reload Register High and Low

These two bytes form the 12-bit Reload value, {PWMRH[3:0], PWMRL[7:0]}. This value

sets the PWM period.

PWM 0–2 Duty Cycle High and Low Byte Registers

The PWM 0–2 H/L Duty Cycle High and Low Byte (PWMxDH and PWMxDL) registers,

shown in Table 46 and Table 47, set the duty cycle of the PWM signal. This 14-bit signed

value is compared to the PWM count value to determine the PWM output. Reads from

these registers always return the values from the temporary holding registers. The PWM

duty cycle value is not used by the PWM generator until the next PWM reload event

occurs.

Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM

period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM

to be ON for the full PWM period.

Table 45. PWM Reload Low Byte Register (PWMRL)

BITS

FIELD

PWMRL

RESET

R/W

ADDR

F2FH

PWM Duty Cycle =

PWM Duty Cycle Value

PWM Reload Value

Table 46. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)

BITS

FIELD

SIGN

Reserved

DUTYH

RESET

0_0000

R/W

ADDR

F30H, F32H, F34H, F36H, F38H, F3AH

ZUSBOPTSC01ZAC 数据表(PDF) 99 Page - Zilog, Inc.

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