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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ZUSBOPTSC01ZAC 数据表(PDF) 92 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 92 Page - Zilog, Inc. |
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92 / 402 page  Pulse-Width Modulator P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 70 PWM Prescaler The prescaler allows the PWM clock signal to be decreased by factors of 1, 2, 4, or 8 with respect to the system clock. The PRES[1:0] bit field in the PWM Control 1 Register (PWMCTL1) controls prescaler operation. This 2-bit PRES field is buffered so that the prescale value only changes upon a PWM reload event. PWM Period and Count Resolution The PWM counter operates in two modes to allow edge-aligned outputs and center- aligned outputs. Figures 8 and 9 illustrate edge- and center-aligned PWM outputs. The period of the PWM outputs, PERIOD, is determined by which mode the PWM counter is operating. The active time of a PWM output is determined by the programmed duty cycle, PWMDC, and the programmed deadband time, PWMDB. The sections that follow these two figures describe the PWM timer modes and the regis- ters that control the duty cycle and deadband time. Figure 8. Edge-Aligned PWM Output Period PWMDB PWMDC PWMDB PWMxH No Deadband PWMxH Deadband Insertion PWMxL PWMxL |
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