ZUSBOPTSC01ZAC datasheet(94/402 Pages) ZILOG

94 / 402 page

Pulse-Width Modulator

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

PWM Duty Cycle Registers

The PWM Duty Cycle registers (PWM0HD, PWM0LD, PWM1HD, PWM1LD,

PWM2HD, PWM2LD) contain a 16-bit signed value, in which bit 15 is the sign bit. The

Duty Cycle value is compared to the current 12-bit unsigned PWM count value. If the

PWM Duty Cycle value is set less than or equal to 0, the PWM output is deasserted for the

full PWM period. If the PWM Duty Cycle value is set to a value greater than the PWM

reload value, the PWM output is asserted for the full PWM period.

Independent and Complementary PWM Outputs

The six PWM outputs are configurable to operate independently, or as three complemen-

tary pairs. Operation as six independent PWM channels is enabled by setting the INDEN

bit in the PWM Control 1 Register (PWMCTL1). The PWEN bit must be cleared to alter

this bit. In independent mode, each PWM output uses its own PWM duty cycle value.

When configured to operate as three complementary pairs, the PWM duty cycle values

PWM0HD, PWM1HD, and PWM2HD control the modulator output. In complementary

output mode, deadband time is also inserted.

The POLx bits in the PWM Control 1 Register (PWMCTL1) select the relative polarity of

the High and Low signals. As illustrated in Figures 8 and 9, when the POLx bits are

cleared to 0, the High PWM output will start in the ON state and transition to the OFF

state when the PWM timer count reaches the programmed duty cycle. The Low PWM

value starts in the OFF state and transitions to the ON state as the PWM timer count

reaches the value in the associated duty cycle register. Alternately, setting the POLx

causes the High output to start in the OFF state and the Low output to start in the ON state.

Manual Off-State Control of PWM Output Channels

Each PWM output can be controlled directly by the modulator logic or set to the OFF

state. To manually set the PWM outputs to the OFF state, set the OUTCTL bit and the asso-

ciated OUTx bits in the PWM Output Control Register (PWMOUT). OFF state control

operates individually by channel. For example, suppressing the single output of a pair

allows the complementary channel to continue operating. Similarly, if the outputs are

operating independently, disabling one output channel has no effect on the other PWM

outputs.

Deadband Insertion

When the PWM outputs are configured to operate as complementary pairs, an 8-bit dead-

band value can be defined in the PWM Deadband Register (PWMDB). Inserting deadband

time causes the modulator to separate the deassertion of one PWM signal from the asser-

tion of its complement. This separation is essential for many motor control applications in

that it prevents simultaneous turn-on of the High and Low drive transistors. The deadband

ZUSBOPTSC01ZAC 数据表(PDF) 94 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 94 Page - Zilog, Inc.

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