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ZUSBOPTSC01ZAC 数据表(PDF) 32 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 32 Page - Zilog, Inc. |
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32 / 402 page ![]() Signal and Pin Descriptions P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 10 Analog ANA[7:0] I Analog Input. These signals are inputs to the analog-to-digital converter (ADC). VREF I/O Voltage buffer output. This signal provides reference voltage for external components. If using the internal reference voltage generator, a 10µF capacitor must be placed on this pin to Ground. CINP I Comparator positive input. CINN I Comparator negative input. COMPOUT O Comparator output. OPINP I Operational amplifier positive input. OPINN I Operational amplifier negative input. OPOUT O Operational amplifier output. Oscillators XIN I The External Crystal Input is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock. XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. This pin must be left unconnected when not using a crystal. On-Chip Debugger DBG I/O Debug. This open-drain pin provides the single-pin control and data interface to the On-Chip Debugger. For operation of the On-chip Debugger, all power pins (VDD) must be supplied with power, and all ground pins (VSS) must be grounded. This pin is open-drain and must have an external pull-up resistor to ensure proper operation. Reset-PWM Fault RESET/FAULT0 I/O RESET input pin generates a Reset or PWM fault when asserted (driven Low). The function selection is determined by the FLTSEL bit of the User Options Bits at Program Memory Address 0001h, and the FAULTSEL bit in the Reset Status and Control Register. Table 1. Signal Descriptions (Continued) Signal Mnemonic I/O Description Caution Caution |
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