ZUSBOPTSC01ZAC datasheet(97/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

PWM Operation in CPU Stop Mode

Z8FMC16100 Series Flash MCU

Product Specification

PWM Operation in CPU Stop Mode

When the eZ8 CPU is operating in STOP mode, the Pulse-Width Modulator is disabled,

because the system clock ceases to operate in STOP mode. The PWM outputs remain in

the same state as they were prior to entering STOP mode. In normal operation, the PWM

outputs must be disabled by the software prior to the CPU entering STOP mode. A fault

condition detected in STOP mode forces the PWM outputs to a predefined OFF state.

Observing the State of PWM Output Channels

The logic value of the PWM outputs can be sampled by reading the PWMIN register. If a

PWM channel pair is disabled (an option bit is not set), the associated PWM outputs are

forced to high-impedance, and can be used as general-purpose inputs.

PWM High and Low Byte Registers

The PWM High and Low Byte (PWMH and PWML) registers, shown in Tables 42 and

43, contain the current 12-bit PWM count value. Reads from PWMH cause the value in

PWML to be stored in a temporary holding register. A read from PWML always returns

this temporary register value.

Writing to the PWM High and Low Byte registers while the PWM is enabled is not rec-

ommended. There are no temporary holding registers for Write operations, so simulta-

neous 12-bit Writes are not possible.

If either the PWM High or Low Byte registers are written during counting, the 8-bit writ-

ten value is placed in the counter (High or Low byte) at the next clock edge. The counter

continues counting from the new value.

Table 42. PWM High Byte Register (PWMH)

BITS

FIELD

Reserved

PWMH

RESET

R/W

ADDR

F2CH

Caution:

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