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ZUSBOPTSC01ZAC 数据表(PDF) 48 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 48 Page - Zilog, Inc. |
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48 / 402 page ![]() Reset and Stop-Mode Recovery P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 26 threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO holds the device in the Reset state. After the supply voltage again exceeds the Power-On Reset voltage threshold and stabi- lized, the device progresses through a full System Reset sequence, as described in the Power-On Reset section. Following Power-On Reset, the POR status bit in the Reset Source register is set to 1. Figure 4 illustrates Voltage Brown-Out operation. Refer to the On-Chip Peripheral AC and DC Electrical Characteristics section on page 265 for the VBO and POR threshold voltages (VVBO and VPOR). The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is controlled by the VBO_AO Option Bit. Refer to the Option Bits chapter for information on configuring VBO_AO. Watch-Dog Timer Reset If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System Reset at time-out if the WDT_RES Option Bit is set to 1. This setting is the default (unpro- grammed) setting of the WDT_RES Option Bit. The WDT status bit in the Reset Status and Control Register is set to signify that the reset was initiated by the Watch-Dog Timer. Figure 4. Voltage Brown-Out Reset Operation Option Bit Counter Delay System Clock Counter Delay Internal RESET Signal Internal Precision Oscillator System Clock VCC = 3.3V VCC = 3.3V VVBO VPOR Program Execution Program Execution Voltage Brown-Out |
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