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ZUSBOPTSC01ZAC 数据表(PDF) 40 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 40 Page - Zilog, Inc. |
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40 / 402 page ![]() Register File Address Map P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 18 F26 PWM Input Sample Register PWMIN 00 86 F27 PWM Output Control Register PWMOUT 00 87 F28 PWM Fault Control Register PWMFCTL 00 85 F29 Current Sense ADC Trigger Control Register PWMSHC 00 87 F2A–B Reserved — XX F2C PWM High Byte Register (PWMH) PWMH 00 75 F2D PWM Low Byte Register (PWML) PWML 00 76 F2E PWM Reload High Byte Register (PWMRH) PWMRH 0F 76 F2F PWM Reload Low Byte Register (PWMRL) PWMRL FF 77 F30 PWM 0 High Side Duty Cycle High Byte PWMH0Dh 00 77 F31 PWM 0 High Side Duty Cycle Low Byte PWMH0DL 00 78 F32 PWM 0 Low Side Duty Cycle High Byte PWML0Dh 00 77 F33 PWM 0 Low Side Duty Cycle Low Byte PWML0DL 00 78 F34 PWM 1 High Side Duty Cycle High Byte PWMH1DH 00 77 F35 PWM 1 High Side Duty Cycle Low Byte PWMH1DL 00 78 F36 PWM 1 Low Side Duty Cycle High Byte PWML1DH 00 77 F37 PWM 1 Low Side Duty Cycle Low Byte PWML1DL 00 78 F38 PWM 2 High Side Duty Cycle High Byte PWMH2DH 00 77 F39 PWM 2 High Side Duty Cycle Low Byte PWMH2DL 00 78 F3A PWM 2 Low Side Duty Cycle High Byte PWML2DH 00 77 F3B PWM 2 Low Side Duty Cycle Low Byte PWML2DL 00 78 F3C–F3F Reserved — XX Table 5. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page # Note: XX = undefined. |
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