ZUSBOPTSC01ZAC datasheet(81/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

IRQ1 Enable High and Low Bit Registers

Z8FMC16100 Series Flash MCU

Product Specification

T0ENH—Timer 1 Interrupt Request Enable High Bit

U0RENH—UART 0 Receive Interrupt Request Enable High Bit

U0TENH—UART 0 Transmit Interrupt Request Enable High Bit

SPIENH—SPI Interrupt Request Enable High Bit

PWMENL—Pulse-Width Modulator Interrupt Request Enable Low Bit

FLTENL—Fault Interrupt Request Enable Low Bit

ADCENL—ADC Interrupt Request Enable Low Bit

CMPENL—Comparator Interrupt Request Enable Low Bit

T0ENL—Timer 0 Interrupt Request Enable Low Bit

U0RENL—UART 0 Receive Interrupt Request Enable Low Bit

U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit

SPIENL—SPI Interrupt Request Enable Low Bit

IRQ1 Enable High and Low Bit Registers

The IRQ1 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority

encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by

setting bits in each register. Table 35 describes the priority control for IRQ1.

Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)

BITS

FIELD

PWMENL

FLTENL

ADCENL

CMPENL

T0ENL

U0RENL

U0TENL

SPIENL

RESET

000

R/W

R/WR/W

ADDR

FC2H

Table 35. IRQ1 Enable and Priority Encoding

IRQ1ENH[x]IRQ1ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

x indicates the register bits from 0 through 7.

ZUSBOPTSC01ZAC 数据表(PDF) 81 Page - Zilog, Inc.

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