ZUSBOPTSC01ZAC datasheet(96/402 Pages) ZILOG

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Pulse-Width Modulator

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

PWM Timer and Fault Interrupts

The PWM generates interrupts to the eZ8 CPU upon any of the following events:

PWM Reload.

The interrupt is generated at the end of a PWM period when a PWM regis-

ter reload occurs (the READY bit is set).

PWM Fault.

A fault condition is indicated by asserting any of the FAULT pins, or by the

assertion of the comparator.

Fault Detection and Protection

The Z8FMC16100 Series Flash MCU contains hardware and software fault controls that

allow rapid deassertion of all enabled PWM output signals. A logic Low on an external

fault pin (FAULT0 or FAULT1), or the assertion of the overcurrent comparator, forces the

PWM outputs to a predefined OFF state.

Similar deassertion of the PWM outputs can be accomplished in software by writing to the

PWMOFF

bit in the PWM Control 0 Register. The PWM counter continues to operate while

the outputs are deasserted (made inactive) due to one of these fault conditions.

The fault inputs can be individually enabled through the PWM Fault Control Register. If a

fault condition is detected and the source is enabled, a fault interrupt is generated. The

PWM Fault Status Register (PWMFSTAT) is read to determine which fault source has

caused the interrupt.

After a fault has been detected, and after the PWM outputs are disabled, modulator control

of the PWM outputs can be reenabled either by software, or by deassertion of the FAULT

input signal. Selection of either method is made via the PWM Fault Control Register

(PWMFCTL). Configuration of the fault modes and reenable methods allows pulse-by-

pulse limiting and hard shutdown. When configured in automatic restart mode, the PWM

outputs are reengaged at beginning of the next PWM cycle (the master timer value is equal

to 0) if all fault signals are deasserted. In a software-controlled restart, all fault inputs must

be deasserted and all fault flags cleared.

The fault input pin is Schmitt-triggered. The input signal from the pin, as well as the com-

parators, pass though an analog filter to reject high-frequency noise.

The logic path from the fault sources to the PWM outputs is asynchronous, which ensures

that the fault inputs will force the PWM outputs to their OFF state, even if the system

clock is stopped.

PWM Operation in CPU Halt Mode

When the eZ8 CPU is operating in HALT mode, the Pulse-Width Modulator continues to

operate, if enabled. To minimize the current in HALT mode, the Pulse-Width Modulator

must be disabled by clearing the PWMEN bit to 0.

ZUSBOPTSC01ZAC 数据表(PDF) 96 Page - Zilog, Inc.

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