ZUSBOPTSC01ZAC datasheet(79/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Interrupt Request 1 Register

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Request 1 Register

The Interrupt Request 1 (IRQ1) Register, shown in Table 31, stores interrupt requests for

both vectored and polled interrupts. When a request is presented to the interrupt controller,

the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled

(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If

interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt

Request 1 Register to determine if any interrupt requests are pending.

Table 31. Interrupt Request 1 Register (IRQ1)

BITS

FIELD

I2CI

Reserved

PC0I

PBI

PA73I

PA62I

PA51I

PA40I

RESET

000

R/W

ADDR

FC3H

Bit

Position

Value

(H)

Description

[7]

I2CI

I2C Interrupt Request

No interrupt request is pending for I2C.

An interrupt request from I2C is awaiting service.

[5]

PC0I

PC0 Interrupt Request — Logic in the Port C GPIO module selects either the

rising or falling edge.

No interrupt request is pending for PC0.

An interrupt request from PC0 is awaiting service.

[4]

PBI

PB3 – PB0 Interrupt Request

No interrupt request is pending for any PB3 – PB0.

An interrupt request from PB3 – PB0 is awaiting service.

[3]

PA73I

PA7 or PA3 Interrupt Request — Logic in the Port A GPIO module selects either

PA7 or PA3 and either rising or falling edge.

No interrupt request is pending for PA7 or PA3

An interrupt request from PA7 or PA3 is awaiting service.

[2]

PA62I

PA6 or PA2 Interrupt Request — Logic in the Port A GPIO module selects either

PA6 or PA2 and either rising or falling edge.

No interrupt request is pending for PA6 or PA2

An interrupt request from PA6 or PA2 is awaiting service.

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