ZUSBOPTSC01ZAC datasheet(91/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

PWM Off State and Output Polarity

Z8FMC16100 Series Flash MCU

Product Specification

PWM Off State and Output Polarity

The default OFF state and the polarity of the PWM outputs are controlled by the PWMHI

and PWMLO option bits. The PWMHI option controls the OFF state and the polarity for the

PWM High outputs 0H, 1H, and 2H. The PWMLO option controls the OFF state and the

polarity for the Low outputs 0L, 1L, and 2L.

The OFF state is the value programmed in the option bit. For example, programming

PWMHI

to a 1 sets the OFF state of PWM0H, 1H, and 2H to a High logic value and the

active state a Low logic value. Conversely, programming PWMHI to a 0 causes the OFF

state to be a Low logic value. PWMLO is programmed in a similar manner.

The relative polarity of the PWM channel pairs is controlled by the POLx bits in the PWM

Control 1 Register (PWMCTL1). These bits do not affect the OFF state programmed by

the option bits. Setting these bits inverts the High and Low of the selected channels. The

relative channel polarity controls the order in which the signals of a given PWM pair tog-

gle. If a POLx bit is reset to zero, the High will first go active at the start of a PWM period.

Alternately., if the bit is set, the Low will go active first. A switching of the POLx bits is

synchronized with the PWM reload event (see below). In complementary mode, the

switch is additionally delayed until the end of the programmed deadband time.

PWM Channel Pair Enable

Following a Power-On Reset (POR), the PWM pins enter a high-impedance state. As the

internal reset proceeds, the PWM outputs are forced to the OFF state as determined by the

PWMHI

and PWMLO OFF state option bits.

The PWM0EN, PWM1EN, and PWM2EN option bits enable the PWM0, PWM1, and PWM2

output pairs, respectively. If a PWM channel pair is not enabled, it remains in a high-

impedance state after reset, and can be used as a general-purpose input.

PWM Reload Event

To prevent erroneous PWM pulse-widths and periods, registers that control the timing of

the output are buffered. Buffering causes all of the PWM compare values to update at the

same time. In other words, the registers that control the duty cycle and clock source pres-

caler only take effect upon a PWM reload event. A PWM reload event can be configured

to occur at the end of each PWM period, or only every 2, 4, or 8 PWM periods by setting

the RELFREQ bits in the PWM Control 1 Register (PWMCTL1). The software must indi-

cate that all new values are ready by setting the READY bit in the PWM Control 0 Register

(PWMCTL0) to 1. After this READY bit has been set to 1, the buffered values take effect

at the next reload event.

ZUSBOPTSC01ZAC 数据表(PDF) 91 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 91 Page - Zilog, Inc.

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