ZUSBOPTSC01ZAC datasheet(80/402 Pages) ZILOG

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Interrupt Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

IRQ0 Enable High and Low Bit Registers

The IRQ0 Enable High and Low Bit registers, shown in Tables 33 and 34, form a priority

encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated

by setting bits in each register. Table 32 describes the priority control for IRQ0.

PWMENH—Pulse-Width Modulator Interrupt Request Enable High Bit

FLTENH—Fault Interrupt Request Enable High Bit

ADCENH—ADC Interrupt Request Enable High Bit

CMPENH—Comparator Interrupt Request Enable High Bit

[1]

PA51I

PA5 or PA1 Interrupt Request — Logic in the Port A GPIO module selects either

PA5 or PA1 and either rising or falling edge.

No interrupt request is pending for PA5 or PA1

An interrupt request from PA5 or PA1 is awaiting service.

[0]

PA40I

PA4 or PA0 Interrupt Request — Logic in the Port A GPIO module selects either

PA4 or PA0 and either rising or falling edge.

No interrupt request is pending for PA4 or PA0

An interrupt request from PA4 or PA0 is awaiting service.

Table 32. IRQ0 Enable and Priority Encoding

IRQ0ENH[x] IRQ0ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

Note: x indicates the register bits from 0 through 7.

Table 33. IRQ0 Enable High Bit Register (IRQ0ENH)

BITS

FIELD

PWMENH

FLTENH

ADCENH CMPENH

T0ENH

U0RENH

U0TENH

SPIENH

RESET

R/W

R/WR/W

R/W

ADDR

FC1H

Bit

Position

Value

(H)

Description

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