ZUSBOPTSC01ZAC datasheet(100/402 Pages) ZILOG

100 / 402 page

Pulse-Width Modulator

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

PWM Control 0 Register

The PWM Control 0 (PWMCTL0) Register, shown in Table 48, controls PWM operation.

Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)

BITS

FIELD

DUTYL

RESET

00H

R/W

ADDR

F31H, F33H, F35H, F37H, F39H, F3BH

Bit

Position

Value

(H)

Description

[7]

SIGN

Duty Cycle Sign

Duty Cycle is a positive two’s complement number.

Duty Cycle is a negative two’s complement number. Output is forced to the off-

state.

[6:0], [7:0]

DUTYH and

DUTYL

PWM Duty Cycle High and Low Bytes

These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5

and 6 of the High Byte are always 0). The value is compared to the current 12-bit

PWM count.

Table 48. PWM Control 0 Register (PWMCTL0)

BITS

FIELD

PWMOFF

OUTCTL

ALIGN

Reserved ADCTRIG Reserved

READY

PWMEN

RESET

000

R/W

ADDR

F20H

ZUSBOPTSC01ZAC 数据表(PDF) 100 Page - Zilog, Inc.

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