ZUSBOPTSC01ZAC datasheet(102/402 Pages) ZILOG

102 / 402 page

Pulse-Width Modulator

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

PWM Control 1 Register

The PWM Control 1 (PWMCTL1) Register, shown in Table 49, controls portions of PWM

operation.

Table 49. PWM Control 1 Register (PWMCTL1)

BITS

FIELD

RLFREQ[1:0]

INDEN

Pol45

Pol23

Pol10

PRES[1:0]

RESET

R/W

ADDR

F21H

Bit

Position

Value

(H)

Description

[7:6]

RLFREQ[1:0]

Reload Event Frequency

This bit field is buffered. Changes to the reload event frequency takes effect at

the end of the current PWM period. Reads always return the bit values from the

temporary holding register.

PWM reload event occurs at the end of every PWM period.

PWM reload event occurs once every 2 PWM periods.

PWM reload event occurs once every 4 PWM periods.

PWM reload event occurs once every 8 PWM periods.

[5]

INDEN

Independent PWM Mode Enable

This bit may only be altered when PWEN (PWMCTL0) cleared.

PWM outputs operate as 3 complementary pairs.

PWM outputs operate as 6 independent channels.

[4]

Pol2

Invert Ouput polarity for channel pair PWM2.

Non-inverted polarity for channel pair PWM2.

[3]

Pol1

Invert Ouput polarity for channel pair PWM1.

Non-inverted polarity for channel pair PWM1.

[2]

Pol0

Invert Ouput polarity for channel pair PWM0.

Non-inverted polarity for channel pair PWM0.

ZUSBOPTSC01ZAC 数据表(PDF) 102 Page - Zilog, Inc.

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