ZUSBOPTSC01ZAC datasheet(83/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Interrupt Control Register

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Control Register

The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the Master Enable

Bit (IRQE) for all interrupts.

IRQE—Interrupt Request Enable

This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)

instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI

instruction, eZ8 CPU acknowledgement of an interrupt request or system exception,

Reset, or direct register write to 0.

0 = Interrupts are disabled.

1 = Interrupts are enabled.

Reserved—Must be 0.

[3]

PA73ENL Port A73 Interrupt Request Enable Low Bit

[2]

PA62ENL Port A62 Interrupt Request Enable Low Bit

[1]

PA51ENL Port A51 Interrupt Request Enable Low Bit

[0]

PA40ENL Port A40 Interrupt Request Enable Low Bit

Table 38. Interrupt Control Register (IRQCTL)

BITS

FIELD

IRQE

Reserved

RESET

000

R/W

RRR

ADDR

FCFH

Bit

Position

Name

Description

ZUSBOPTSC01ZAC 数据表(PDF) 83 Page - Zilog, Inc.

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