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ZUSBOPTSC01ZAC 数据表(PDF) 50 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 50 Page - Zilog, Inc. |
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50 / 402 page ![]() Reset and Stop-Mode Recovery P R E L I M I N A R Y PS024604-1005 Z8 Encore!® Motor Control Flash MCUs Product Specification 28 Stop-Mode Recovery STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the Low-Power Modes chapter on page 31 for detailed STOP mode information. During Stop- Mode Recovery, the device is held in reset for 66 cycles of the Internal Precision Oscilla- tor. Stop-Mode Recovery only affects the contents of the Reset Status and Control Regis- ter and Oscillator Control Register. Stop-Mode Recovery does not affect any other values in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and general-purpose RAM. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002h and 0003h and loads that value into the Program Counter. Program execution begins at the Reset vec- tor address. Following Stop-Mode Recovery, the STOP bit in the Reset Status and Control Register is set to 1. Table 8 lists the Stop-Mode Recovery sources and resulting actions. The text following provides more detailed information on each of the Stop-Mode Recov- ery sources Stop-Mode Recovery Using Watch-Dog Timer Time-Out If the Watch-Dog Timer times out during STOP mode, the device undergoes a Stop-Mode Recovery sequence. In the Reset Status and Control Register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate a System Exception upon time- out, the eZ8 CPU services the Watch-Dog Timer System Exception following the normal Stop-Mode Recovery sequence. Stop-Mode Recovery Using a GPIO Port Pin Transition Each of the GPIO port pins may be configured as a Stop-Mode Recovery input source. On any GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates Stop-Mode Recovery. The GPIO Stop- Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In the Reset Status and Control Register, the STOP bit is set to 1. Table 8. Stop-Mode Recovery Sources and Resulting Action Operating Mode Stop-Mode Recovery Source Action Stop Mode Watch-Dog Timer time-out when configured for Reset Stop-Mode Recovery Watch-Dog Timer time-out when configured for System Exception Stop-Mode Recovery followed by WDT System Exception Data transition on any GPIO port pin enabled as a Stop-Mode Recovery source Stop-Mode Recovery |
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