ZUSBOPTSC01ZAC datasheet(308/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8 Encore!® Motor Control Flash MCUs

Product Specification

286

eZ8 CPU Instruction Summary

Table 165 summarizes the eZ8 CPU instructions. The table identifies the addressing

modes employed by the instruction, the effect upon the Flags Register, the number of CPU

clock cycles required for the instruction fetch, and the number of CPU clock cycles

required for the instruction execution.

RLC

dst

Rotate Left through Carry

dst

Rotate Right

RRC

dst

Rotate Right through Carry

SRA

dst

Shift Right Arithmetic

SRL

dst

Shift Right Logical

SWAP

dst

Swap Nibbles

Table 165. eZ8 CPU Instruction Summary

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

ADC dst, src

dst

← dst + src + C

rIr

RIR

RIM

ADCX dst, src

dst

← dst + src + C

ER ER

Note: Flags Notation:

* = Value is a function of the result of the operation.

– = unaffected.

X = undefined.

0 = reset to 0.

1 = set to 1.

Table 164. Rotate and Shift Instructions (Continued)

Mnemonic

Operands

Instruction

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