EDBA164B4PR-1DITF-R datasheet(4/152 Pages) MICRON

4 / 152 page

Truth Tables ................................................................................................................................................... 94

Absolute Maximum Ratings ........................................................................................................................... 102

Input/Output Capacitance ............................................................................................................................. 102

Electrical Specifications – IDD Specifications and Conditions ........................................................................... 103

AC and DC Operating Conditions ................................................................................................................... 106

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 107

VREF Tolerances ......................................................................................................................................... 108

Input Signal .............................................................................................................................................. 110

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 112

Single-Ended Requirements for Differential Signals .................................................................................... 113

Differential Input Crosspoint Voltage ......................................................................................................... 115

Input Slew Rate ......................................................................................................................................... 116

Output Characteristics and Operating Conditions ........................................................................................... 116

Single-Ended Output Slew Rate .................................................................................................................. 117

Differential Output Slew Rate ..................................................................................................................... 118

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 120

Output Driver Impedance .............................................................................................................................. 121

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 122

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 123

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 123

Clock Specification ........................................................................................................................................ 126

tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 128

Clock Period Jitter .......................................................................................................................................... 128

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 128

Cycle Time Derating for Core Timing Parameters ........................................................................................ 129

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 129

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 129

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 129

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 130

Refresh Requirements Parameters .................................................................................................................. 131

AC Timing ..................................................................................................................................................... 131

CA and CS_n Setup, Hold, and Derating .......................................................................................................... 137

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 145

Revision History ............................................................................................................................................ 152

Rev. F – 08/16 ............................................................................................................................................ 152

Rev. E – 05/16 ............................................................................................................................................ 152

Rev. D – 03/16 ............................................................................................................................................ 152

Rev. C – 02/16 ............................................................................................................................................ 152

Rev. B – 01/15 ............................................................................................................................................ 152

Rev. A – 09/14 ............................................................................................................................................ 152

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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