EDBA164B4PR-1DITF-R datasheet(55/152 Pages) MICRON

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WRITEs Interrupted by a WRITE

A burst WRITE can only be interrupted by another WRITE with a 4-bit burst boundary,

provided that tCCD (MIN) is met.

A WRITE burst interrupt can occur on even clock cycles after the initial WRITE com-

mand, provided that tCCD (MIN) is met.

Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2

Bank m

col addr a

Col addr a

WRITE

NOP

CK#

CA[9:0]

CMD

DQS#

DQS

WL = 1

Transitioning data

WRITE

NOP

tCCD = 2

NOP

IN B0

IN B1

IN B2

IN B3

IN B4

IN B5

IN B6

IN B7

IN A0

IN A1

IN A2

IN A3

NOP

Bank n

col addr b

Col addr b

Notes:

1. WRITEs can only be interrupted by other WRITEs or the BST command.

2. The effective burst length of the first WRITE equals two times the number of clock cycles

between the first WRITE and the interrupting WRITE.

BURST TERMINATE Command

The BURST TERMINATE (BST) command is initiated with CS_n LOW, CA0 HIGH, CA1

HIGH, CA2 LOW, and CA3 LOW at the rising edge of the clock. A BST command can be

issued only to terminate an active READ or WRITE burst. Therefore, a BST command

can be issued only up to and including BL/2 - 1 clock cycles after a READ or WRITE

command. The effective burst length of a READ or WRITE command truncated by a

BST command is as follows:

• Effective burst length = 2 × (number of clock cycles from the READ or WRITE com-

mand to the BST command).

• If a READ or WRITE burst is truncated with a BST command, the effective burst length

of the truncated burst should be used for BL when calculating the minimum READ-

to-WRITE or WRITE-to-READ delay.

• The BST command only affects the most recent READ or WRITE command. The BST

command truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the ris-

ing edge of the clock where the BST command is issued. The BST command truncates

an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the

BST command is issued.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

BURST TERMINATE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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