EDBA164B4PR-1DITF-R datasheet(42/152 Pages) MICRON

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Table 43: Reserved Mode Registers

Mode Reg-

ister

Address

Restriction

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

MR[18:19]

MA[7:0]

12h–13h

RFU

Reserved

MR[20:31]

14h–1Fh

NVM1

MR[33:39]

21h–27h

DNU1

MR[41:47]

29h–2Fh

MR[48:62]

30h–3Eh

RFU

MR[64:126]

40h–7Eh

RFU

MR127

7Fh

DNU

MR[128:190]

80h–BEh

RVU1

MR191

BFh

DNU

MR[192:254]

C0h–FEh

RVU

MR255

FFh

DNU

Note:

1. NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use.

Table 44: MR32 DQ Calibration Pattern A (MA[7:0] = 20H)

MR32 Reads

Reads to MR32 return DQ Calibration Pattern A

Table 45: MR40 DQ Calibration Pattern B (MA[7:0] = 28H)

MR40 Reads

Reads to MR40 return DQ Calibration Pattern B

Table 46: MR63 RESET (MA[7:0] = 3Fh) – MRW Only

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Note:

1. For additional information on MRW RESET see MODE REGISTER WRITE Command.

Commands and Timing

The setup and hold timings shown in the figures below apply for all commands.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Commands and Timing

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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