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EDBA164B4PR-1DITF-R 数据表(PDF) 92 Page - Micron Technology |
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EDBA164B4PR-1DITF-R 数据表(HTML) 92 Page - Micron Technology |
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92 / 152 page ![]() Figure 66: MRR Command to Power-Down Entry CK_c CKE1 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ DQS_c MRR D OUT DOUT DOUT DOUT RL tISCKE CK_t DQS_t Note: 1. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the MRR command is registered. Figure 67: MRW Command to Power-Down Entry CK_c CKE1 CMD tMRW MRW tISCKE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK_t Note: 1. CKE can be registered LOW tMRW after the clock on which the MRW command is regis- tered. Deep Power-Down Deep power-down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command must be driven in the clock cycle following power-down entry. CKE must not go LOW while MRR or MRW operations are in progress. CKE can go LOW while other operations such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress; however, deep power-down IDD specifications will not be applied until those operations com- plete. The contents of the array will be lost upon entering DPD mode. In DPD mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled within the device. VREFDQ can be at any level between 0 and VDDQ, and VREFCA can be at any level between 0 and VDD2 during DPD. All power supplies (including VREF) must be within the specified limits prior to exiting DPD (see AC and DC Operating Conditions). 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Deep Power-Down 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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