EDBA164B4PR-1DITF-R datasheet(30/152 Pages) MICRON

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Figure 12: Voltage Ramp and Initialization Sequence

RESET

MRR

ZQ_CAL

Valid

CK_c

tINIT0

tINIT1

tINIT3

tINIT4

tZQINIT

tINIT5

tISCKE

tINIT2

CK_t

Supplies

CKE

Note:

1. High-Z on the CA bus indicates valid NOP.

Table 10: Initialization Timing Parameters

Parameter

Value

Unit

Comment

Min

Max

tINIT0

–

Maximum voltage ramp time

tINIT1

100

–

Minimum CKE LOW time after completion of voltage ramp

tINIT2

–

tCK

Minimum stable clock before first CKE HIGH

tINIT3

200

–

μs

Minimum idle time after first CKE assertion

tINIT4

–

μs

Minimum idle time after RESET command

tINIT5

–

μs

Maximum duration of device auto initialization

tZQINIT

–

μs

ZQ initial calibration (S4 devices only)

tCKb

100

Clock cycle time during boot

Note:

1. The tINIT0 maximum specification is not a tested limit and should be used as a general

guideline. For voltage ramp times exceeding tINIT0 MAX, contact the factory.

Initialization After RESET (Without Voltage Ramp)

If the RESET command is issued before or after the power-up initialization sequence,

the reinitialization procedure must begin at Td.

Power-Off Sequence

While powering off, CKE must be held LOW (≤0.2 × VDD2); all other inputs must be be-

tween VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Power-Off Sequence

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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