EDBA164B4PR-1DITF-R datasheet(77/152 Pages) MICRON

77 / 152 page

Following a WRITE command, the MRR command must not be issued before WL + 1 +

BL/2 + RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is trunca-

ted with a BST command, the effective burst length of the truncated burst should be

used for the BL value.

Figure 50: READ to MRR Timing – RL = 3, tMRR = 2

Bank m

col addr a

Col addr a

READ

NOP2

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

DQ[7:0]

DQ[MAX:8]

RL = 3

Transitioning data

Undefined

tMRR = 2

BL/21

OUT B

OUT A0

OUT A1

OUT A2

OUT A3

OUT A0

OUT A1

OUT A2

OUT A3

Valid

MRR

Notes:

1. The minimum number of clock cycles from the burst READ command to the MRR com-

mand is BL/2.

2. Only the NOP command is supported during tMRR.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

MODE REGISTER READ

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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