EDBA164B4PR-1DITF-R datasheet(59/152 Pages) MICRON

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Table 47: Bank Selection for PRECHARGE by Address Bits

AB (CA4r)

BA2 (CA9r)

BA1 (CA8r)

BA0 (CA7r)

Precharged Bank(s) 4-

Bank Device

Precharged Bank(s) 8-

Bank Device

0000

Bank 0 only

0001

Bank 1 only

0010

Bank 2 only

0011

Bank 3 only

0100

Bank 0 only

Bank 4 only

0101

Bank 1 only

Bank 5 only

0110

Bank 2 only

Bank 6 only

0111

Bank 3 only

Bank 7 only

Don’t Care

All banks

READ Burst Followed by PRECHARGE

For the earliest possible precharge, the PRECHARGE command can be issued BL/2

clock cycles after a READ command. A new bank ACTIVATE command can be issued to

the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE com-

mand cannot be issued until after tRAS is satisfied.

The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog

time from the rising clock edge that initiates the last 4-bit prefetch of a READ com-

mand. tRTP begins BL/2 - 2 clock cycles after the READ command.

If the burst is truncated by a BST command, the effective BL value is used to calculate

when tRTP begins.

Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2

Bank m

col addr a Col addr a

READ

NOP

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

RL = 3

tRP

Transitioning data

NOP

PRECHARGE

NOP

tRTP

NOP

OUT A4

OUT A5

OUT A6

OUT A7

OUT A0

OUT A1

OUT A2

OUT A3

ACTIVATE

NOP

Bank m

row addr

Row addr

BL/2

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

PRECHARGE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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