EDBA164B4PR-1DITF-R datasheet(24/152 Pages) MICRON

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Ball Descriptions

The ball/pad description table below is a comprehensive list of signals for the device

family. All signals listed may not be supported on this device. See Ball Assignments for

information specific to this device.

Table 9: Ball/Pad Descriptions

Symbol

Type

Description

CA[9:0]_A,

CA[9:0]_B

Input

Command/address inputs: Provide the command and address inputs according to the

command truth table. A separate CA[9:0] is provided for each channel (A and B).

CK_t_A, CK_t_B

CK_c_A, CK_c_B

Input

Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling

edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are

referenced to clock. A separate CK_t/CK_c is provided for each channel (A and B).

CKE[1:0]_A,

CKE[1:0]_B

Input

Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,

input buffers, and output drivers. Power-saving modes are entered and exited via CKE

transitions. CKE is considered part of the command code. CKE is sampled on the rising

edge of CK. A separate CKE is provided for each channel (A and B).

CS[1:0]_n_A,

CS[1:0]_n_B

Input

Chip select: Considered part of the command code and is sampled on the rising edge

of CK. A separate CS_n is provided for each channel (A and B).

DM[3:0]_A,

DM[3:0]_B

Input

Input data mask: Input mask signal for write data. Although DM balls are input-only,

the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each

of the four data bytes, respectively. A separate DM[3:0] is provided for each channel (A

and B).

DQ[31:0]_A,

DQ[31:0]_B

I/O

Data input/output: Bidirectional data bus. A separate DQ[11:0] is provided for each

channel (A and B).

DQS[3:0]_t_A,

DQS[3:0]_t_B,

DQS[3:0]_c_A,

DQS[3:0]_c_B

I/O

Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t

and DQS_c). It is edge-aligned output with read data and centered input with write da-

ta. DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively. A sepa-

rate DQS[3:0]_t and DQS[3:0]_c is provided for each channel (A and B).

VDDQ_A, VDDQ_B

Supply

DQ power supply: Isolated on the die for improved noise immunity.

VSSQ_A/B

Supply

DQ ground: Isolated on the die for improved noise immunity.

VDD1 _A/B

Supply

Core power: Supply 1.

VDD2_A/B

Supply

Core power: Supply 2.

VSS_A/B

Supply

Common ground.

VREFCA_A, VREFCA_B

VREFDQ_A, VREFDQ_B

Supply

Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ is

reference for DQ input buffers. A separate VREFCA and VREFDQ provided for each channel

(A and B).

ZQ_A, ZQ_B

Reference

External reference ball for output drive calibration: This ball is tied to an external

240

Ω resistor (RZQ), which is tied to V

SSQ. A separate ZQ is provided for each channel (A

and B).

–

Not usable: Do not connect.

–

No connect: Not internally connected.

(NC)

–

No connect: Balls indicated as (NC) are no connects; however, they could be connected

together internally.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Ball Descriptions

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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