EDBA164B4PR-1DITF-R datasheet(5/152 Pages) MICRON

5 / 152 page

List of Figures

Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2

Figure 2: Dual Die Single Rank, Dual Channel Package Block Diagram ............................................................. 16

Figure 3: Quad Die Dual Rank, Dual Channel Package Block Diagram ............................................................. 17

Figure 4: 216-Ball FBGA (12mm x 12mm x 0.8mm) – EDB8164B4PR, EDB8164B4PT ......................................... 18

Figure 5: 216-Ball FBGA (12mm x 12mm x 1.0mm) – EDBA164B2PR ................................................................ 19

Figure 6: 220-Ball FBGA (14mm x 14mm x 0.7mm) – EDB8164B4PK ................................................................ 20

Figure 7: 216-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 21

Figure 8: 220-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 22

Figure 9: 216-Ball Dual-Channel FBGA – 4 x 4Gb Die ...................................................................................... 23

Figure 10: Functional Block Diagram ............................................................................................................. 26

Figure 11: Simplified State Diagram ............................................................................................................... 27

Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 30

Figure 13: Command and Input Setup and Hold ............................................................................................. 43

Figure 14: CKE Input Setup and Hold ............................................................................................................. 43

Figure 15: ACTIVATE Command .................................................................................................................... 44

Figure 16: tFAW Timing (8-Bank Devices) ....................................................................................................... 45

Figure 17: READ Output Timing – tDQSCK (MAX) ........................................................................................... 46

Figure 18: READ Output Timing – tDQSCK (MIN) ........................................................................................... 46

Figure 19: Burst READ – RL = 5, BL = 4, tDQSCK > tCK ..................................................................................... 47

Figure 20: Burst READ – RL = 3, BL = 8, tDQSCK < tCK ..................................................................................... 47

Figure 21: tDQSCKDL Timing ........................................................................................................................ 48

Figure 22: tDQSCKDM Timing ....................................................................................................................... 49

Figure 23: tDQSCKDS Timing ......................................................................................................................... 50

Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 51

Figure 25: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2 .............................................................................. 51

Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2 ................................................................. 52

Figure 27: Data Input (WRITE) Timing ........................................................................................................... 53

Figure 28: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 53

Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 54

Figure 30: Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2 ............................................................................ 54

Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2 ................................................................ 55

Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 56

Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 57

Figure 34: Data Mask Timing ......................................................................................................................... 57

Figure 35: Write Data Mask – Second Data Bit Masked .................................................................................... 58

Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 ................................ 59

Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 ................................ 60

Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 61

Figure 39: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 ........................................ 62

Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 63

Figure 41: tSRF Definition .............................................................................................................................. 67

Figure 42: Regular Distributed Refresh Pattern ............................................................................................... 69

Figure 43: Supported Transition from Repetitive REFRESH Burst .................................................................... 70

Figure 44: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 71

Figure 45: Recommended Self Refresh Entry and Exit ..................................................................................... 72

Figure 46: All-Bank REFRESH Operation ........................................................................................................ 73

Figure 47: Per-Bank REFRESH Operation ....................................................................................................... 73

Figure 48: SELF REFRESH Operation .............................................................................................................. 74

Figure 49: MRR Timing – RL = 3, tMRR = 2 ...................................................................................................... 76

Figure 50: READ to MRR Timing – RL = 3, tMRR = 2 ......................................................................................... 77

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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