EDBA164B4PR-1DITF-R datasheet(54/152 Pages) MICRON

54 / 152 page

Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4

Bank m

col addr a

Col addr a

WRITE

NOP

CK#

CA[9:0]

CMD

DQS#

DQS

WL = 1

RL = 3

tWTR

Transitioning data

NOP

READ

IN A0

IN A1

IN A2

IN A3

NOP

Bank n

col addr b

Col addr b

Notes:

1. The minimum number of clock cycles from the burst WRITE command to the burst READ

command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].

2. tWTR starts at the rising edge of the clock after the last valid input data.

3. If a WRITE burst is truncated with a BST command, the effective burst length of the

truncated WRITE burst should be used as BL to calculate the minimum WRITE-to-READ

delay.

Figure 30: Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2

Bank m

col addr a

Col addr a

WRITE

NOP

CK#

CA[9:0]

CMD

DQS#

DQS

WL = 1

Transitioning data

WRITE

NOP

tCCD = 2

NOP

IN B0

IN B1

IN B2

IN B3

IN A0

IN A1

IN A2

IN A3

NOP

Bank n

col addr b

Col addr b

Note:

1. The seamless burst WRITE operation is supported by enabling a WRITE command every

other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight

clocks for BL = 16 operation. This operation is supported for any activated bank.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Burst WRITE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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