EDBA164B4PR-1DITF-R datasheet(57/152 Pages) MICRON

57 / 152 page

Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16

Bank n

col addr a

Col addr a

READ

NOP

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

RL = 3

Transitioning data

BST prohibited

NOP

BST

NOP

RL × tCK + tDQSCK + tDQSQ

NOP

OUT A4

OUT A5

OUT A6

OUT A7

OUT A0

OUT A1

OUT A2

OUT A3

NOP

Notes:

1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after

the rising edge of the clock where the BST command is issued.

2. BST can only be issued an even number of clock cycles after the READ command.

3. Additional BST commands are not supported after T4 and must not be issued until after

the next READ or WRITE command.

Write Data Mask

On the LPDDR2 device, one write data mask (DM) pin for each data byte (DQ) is sup-

ported, consistent with the implementation on LPDDR SDRAM. Each DM can mask its

respective DQ for any given cycle of the burst. Data mask timings match data bit timing,

but are inputs only. Internal data mask loading is identical to data bit loading to ensure

matched system timing.

Figure 34: Data Mask Timing

DQS_c

DQS_t

tDS

tDH

tDS

IL(AC)

IH(AC)

IL(AC)

IH(AC)

IL(DC)

IH(DC)

tDH

IL(DC)

IH(DC)

Don’t Care

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Write Data Mask

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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