EDBA164B4PR-1DITF-R datasheet(52/152 Pages) MICRON

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READs Interrupted by a READ

A burst READ can be interrupted by another READ with a 4-bit burst boundary, provi-

ded that tCCD is met.

Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2

READ

NOP

CK#

CA[9:0]

CMD

DQS#

DQS

RL = 3

Transitioning data

READ

NOP

tCCD = 2

NOP

OUT B0

OUT B1

OUT B2

OUT B3

OUT B4

OUT B5

OUT A0

OUT A1

OUT A2

OUT A3

NOP

Bank n

col addr a

Col addr a

Bank n

col addr b

Col addr b

Note:

1. READs can only be interrupted by other READs or the BST command.

Burst WRITE Command

The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2

LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and

CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is

defined from the rising edge of the clock on which the WRITE command is issued to the

rising edge of the clock from which the tDQSS delay is measured. The first valid data

must be driven WL × tCK + tDQSS from the rising edge of the clock from which the

WRITE command is issued. The data strobe signal (DQS) must be driven LOW tWPRE

prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to

the associated edge of the DQS and held valid until tDH after that edge. Burst data is

sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is com-

pleted. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE

command to the same bank can be issued.

Pin input timings are measured relative to the crosspoint of DQS and its complement,

DQS#.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Burst WRITE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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