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EDBA164B4PR-1DITF-R 数据表(PDF) 98 Page - Micron Technology |
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EDBA164B4PR-1DITF-R 数据表(HTML) 98 Page - Micron Technology |
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98 / 152 page  Table 56: Current State Bank n to Command to Bank n Truth Table (Continued) Notes 1–5 apply to all parameters and conditions Current State Command Operation Next State Notes Reading READ Select column and start new read burst Reading 11, 12 WRITE Select column and start write burst Writing 11, 12, 13 BST Read burst terminate Active 14 Writing WRITE Select column and start new write burst Writing 11, 12 READ Select column and start read burst Reading 11, 12, 15 BST Write burst terminate Active 14 Power-on RESET Begin device auto initialization Resetting 7, 9 Resetting MRR Read value from mode register Resetting MR reading Notes: 1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP has been met, if the previous state was power-down. 2. All states and sequences not shown are illegal or reserved. 3. Current state definitions: Idle: The bank or banks have been precharged, and tRP has been met. Active: A row in the bank has been activated, and tRCD has been met. No data bursts or accesses and no register accesses are in progress. Reading: A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. Writing: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. 4. These states must not be interrupted by a command issued to the same bank. NOP com- mands or supported commands to the other bank must be issued on any clock edge oc- curring during these states. Supported commands to the other banks are determined by that bank’s current state and the definitions given here. Precharge: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank is in the idle state. Row activate: Starts with registration of an ACTIVATE command and ends when tRCD is met. After tRCD is met, the bank is in the active state. READ with AP enabled: Starts with registration of a READ command with auto pre- charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state. WRITE with AP enabled: Starts with registration of a WRITE command with auto pre- charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state. 5. These states must not be interrupted by any executable command. NOP commands must be applied to each rising clock edge during these states. Refresh (per bank): Starts with registration of a REFRESH (per bank) command and ends when tRFCpb is met. After tRFCpb is met, the bank is in the idle state. Refresh (all banks): Starts with registration of a REFRESH (all banks) command and ends when tRFCab is met. After tRFCab is met, the device is in the all banks idle state. Idle MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the device is in the all banks idle state. 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Truth Tables 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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