LSM6DSTX datasheet(167/175 Pages) STMICROELECTRONICS

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Table 109. 117. STATUS_MASTER_MAINPAGE register ............................................... 72

Table 110. STATUS_MASTER_MAINPAGE register description .......................................... 72

Table 111. FIFO_STATUS1 register .............................................................. 72

Table 112. FIFO_STATUS2 register .............................................................. 73

Table 113. FIFO_STATUS2 register description ...................................................... 73

Table 114. TIMESTAMP output registers .......................................................... 73

Table 115. TIMESTAMP output register description ................................................... 73

Table 116. UI_STATUS_REG_OIS register ......................................................... 74

Table 117. UI_STATUS_REG_OIS register description ................................................. 74

Table 118. UI_OUTX_L_G_OIS register ........................................................... 74

Table 119. UI_OUTX_H_G_OIS register........................................................... 74

Table 120. UI_OUTX_H_G_OIS register description................................................... 74

Table 121. UI_OUTY_L_G_OIS register ........................................................... 74

Table 122. UI_OUTY_H_G_OIS register........................................................... 74

Table 123. UI_OUTY_H_G_OIS register description................................................... 74

Table 124. UI_OUTZ_L_G_OIS register ........................................................... 75

Table 125. UI_OUTZ_H_G_OIS register ........................................................... 75

Table 126. UI_OUTZ_H_G_OIS register description................................................... 75

Table 127. UI_OUTX_L_A_OIS register ........................................................... 75

Table 128. UI_OUTX_H_A_OIS register ........................................................... 75

Table 129. UI_OUTX_H_A_OIS register description ................................................... 75

Table 130. UI_OUTY_L_A_OIS register ........................................................... 75

Table 131. UI_OUTY_H_A_OIS register ........................................................... 75

Table 132. UI_OUTY_H_A_OIS register description ................................................... 75

Table 133. UI_OUTZ_L_A_OIS register ........................................................... 76

Table 134. UI_OUTZ_H_A_OIS register ........................................................... 76

Table 135. UI_OUTZ_H_A_OIS register description ................................................... 76

Table 136. TAP_CFG0 register ................................................................. 76

Table 137. TAP_CFG0 register description ......................................................... 76

Table 138. TAP_CFG1 register ................................................................. 77

Table 139. TAP_CFG1 register description ......................................................... 77

Table 140. TAP priority decoding ................................................................ 77

Table 141. TAP_CFG2 register ................................................................. 77

Table 142. TAP_CFG2 register description ......................................................... 77

Table 143. TAP_THS_6D register ............................................................... 78

Table 144. TAP_THS_6D register description ....................................................... 78

Table 145. Threshold for D4D/D6D function ........................................................ 78

Table 146. TAP_DUR register .................................................................. 78

Table 147. TAP_DUR register description .......................................................... 78

Table 148. WAKE_UP_THS register.............................................................. 79

Table 149. WAKE_UP_THS register description ..................................................... 79

Table 150. WAKE_UP_DUR register ............................................................. 79

Table 151. WAKE_UP_DUR register description ..................................................... 79

Table 152. FREE_FALL register ................................................................ 80

Table 153. FREE_FALL register description ........................................................ 80

Table 154. Threshold for free-fall function .......................................................... 80

Table 155. MD1_CFG register .................................................................. 81

Table 156. MD1_CFG register description.......................................................... 81

Table 157. MD2_CFG register .................................................................. 82

Table 158. MD2_CFG register description.......................................................... 82

Table 159. I3C_BUS_AVB register ............................................................... 83

Table 160. I3C_BUS_AVB register description....................................................... 83

Table 161. INTERNAL_FREQ_FINE register........................................................ 83

Table 162. INTERNAL_FREQ_FINE register description................................................ 83

Table 163. UI_INT_OIS register................................................................. 84

LSM6DSTX

List of tables

DS14039 - Rev 1

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