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IP101G-DS-R01 数据表(PDF) 14 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 14 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
14/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
IP101GA
Pin no.
Label
Type
Reset
Description
State
code.
31,30 MDI_RP
MDI_RN
I/O
I/O
Hi-Z Receive Input Pair: Differential pair shared by
100Base-TX and 10Base-T modes.
Clock and Miscellaneous Pins
47
X2
O
O
25MHz Crystal Output:
Connects to crystal to provide
the 25MHz output. It must be left open when X1 is driven
with an external 25MHz oscillator.
46
X1
I
I
25MHz Crystal Input:
Connects to crystal to provide the
25MHz crystal input. If a 25MHz oscillator is used,
connect X1 to the oscillator’s output. If a 50MHz clock is
applied to pin7 TXCLK/50M_CLKI, X1 must be
connected to GND or AGND33.
42
RESET_N
I
I
(PU)
RESET_N:
Enable a low status signal will reset the chip.
For a complete reset function. 25MHz clock (x1) must be
active for a minimum of 10 clock cycles before the rising
edge of RESET_N. Chip will be able to operate after
2.5ms delay of the rising edge of RESET_N. The 2.5ms
extension is to ensure the stability of system power.
28
ISET
I
I
Bandgap
Circuit
Resistor:
This pin should be
connected to GND via a 6.19KΩ (1%) resistor to define
the standard current of the internal circuit.
48
INTR
OD
Hi-Z Interrupt: Programmable Interrupt Output, this is an
open drain output, and an external pulled-up resistor is
needed for normal mode operation. Another operation
mode is Rx to Tx loopback debugging test (reflect on
Register P1R23[13] RX2TX_LPBK) when connect INTR
pin to GND.
9
LED0/PHY_AD0
O/LI
Hi-Z LED 0 and PHY Address [0]
LED 0
LED mode
1
2
LED0 Link
Link /ACT(blinking)
10
LED1/PHY_AD1
O/LI
Hi-Z LED 1 and PHY Address [1]
LED1
LED mode
1
2
LED1 Duplex
Duplex /COL (blinking)
12
LED2/PHY_AD2
O/LI
Hi-Z LED 2 and PHY Address [2]
LED2
LED mode
1
2
LED2 10M Link /ACT
10M Link
13
LED3/PHY_AD3
O/LI
(PD)
Hi-Z LED 3 and PHY Address [3]
LED3
LED mode
1
2
LED3 100M Link /ACT
100M Link
27
TEST_ON
I
I
Test Enable:
Set this pin to high to enable Test mode.



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