| 数据搜索系统,热门电子元器件搜索 |
|
IP101G-DS-R01 数据表(PDF) 2 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
IP101G-DS-R01 数据表(HTML) 2 Page - List of Unclassifed Manufacturers |
|
2 / 65 page ![]() IP101G Data Sheet 2/65 January 14, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Table Of Contents Table Of Contents.................................................................................................................................... 2 List of Figures .......................................................................................................................................... 4 List of Tables............................................................................................................................................ 5 Revision History....................................................................................................................................... 6 Features comparison between IP101G and IP101A/IP101AH ............................................................... 7 Transmit and Receive Data Path Block Diagram .................................................................................... 8 1 Pin diagram ...................................................................................................................................... 9 2 Dice pad information .......................................................................................................................11 3 Pin description................................................................................................................................12 3.1 IP101GA pin description .................................................................................................... 12 3.2 IP101GR/GRI pin description............................................................................................. 16 4 Register Descriptions ..................................................................................................................... 19 4.1 Register Page mode Control Register ............................................................................... 20 4.2 MII Registers...................................................................................................................... 20 4.3 MMD Control Register ....................................................................................................... 30 4.4 MMD Data Register ........................................................................................................... 31 4.5 RX Counter Register.......................................................................................................... 34 4.6 LED Pin Control Register................................................................................................... 35 4.7 WOL+ Control Register...................................................................................................... 35 4.8 UTP PHY Specific Control Register ................................................................................... 38 4.9 Digital IO Pin Control Register ........................................................................................... 39 5 Function Description....................................................................................................................... 41 5.1 Major Functional Block Description ................................................................................... 41 5.1.1 Transmission Description...................................................................................... 41 5.1.2 MII and Management Control Interface ................................................................ 42 5.1.3 RMII Interface ....................................................................................................... 43 5.1.4 Flexible Clock Source ........................................................................................... 45 5.1.5 Auto-Negotiation and Related Information............................................................ 45 5.1.6 Auto-MDIX function............................................................................................... 46 5.2 PHY Address Configuration ............................................................................................... 46 5.3 Power Management Tool ................................................................................................... 47 5.3.1 Auto Power Saving Mode ..................................................................................... 47 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) ..................................................... 48 5.3.3 Force power down ................................................................................................ 48 5.3.4 WOL+ operation mode.......................................................................................... 48 5.4 LED Mode Configuration.................................................................................................... 52 5.5 LED Blink Timing................................................................................................................ 52 5.6 Repeater Mode .................................................................................................................. 52 5.7 Interrupt.............................................................................................................................. 52 5.8 Miscellaneous .................................................................................................................... 52 5.9 Serial Management Interface............................................................................................. 53 5.10 Fiber Mode Setting............................................................................................................. 54 5.11 Jumbo Frame..................................................................................................................... 54 6 Layout Guideline ............................................................................................................................ 55 6.1 General Layout Guideline .................................................................................................. 55 6.2 Twisted Pair recommendation............................................................................................ 55 7 Electrical Characteristics ................................................................................................................ 56 7.1 Absolute Maximum Rating ................................................................................................. 56 7.2 DC Characteristics ............................................................................................................. 56 7.3 Crystal Specifications......................................................................................................... 57 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |