IP101G-DS-R01 datasheet(48/65 Pages) ETC

48 / 65 page

IP101G

Data Sheet

48/65

January 14, 2014

IP101G-DS-R01

5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet)

In order to enter this mode, the PHY part should declare the EEE capability during the

auto-negotiation phase, and then send a LLDP to the link partner to indicate the wakeup time.

If both ends of the cable support EEE, IP101G can enter Low Power Idle mode per the request

from the higher layer (such as the command from CPU or MAC layer). There are 2 methods to activate

Low Power Idle Mode: the MII/RMII bus coming from MAC layer and the MII register control coming from

MDC/MDIO serial bus.

For legacy Ethernet MAC, the MII/RMII does not provide any command regarding EEE. When used

in conjunction with these MACs, IP101G provides a MII register that allows the designer to activate the

Low Power Idle mode.

It’s the higher layer’s responsibility to memorize the link partner’s wakeup time and wakeup the link

partner before sending data. The higher layer means a mechanism that can evaluate the packet buffer

utilization and wake the link partner before sending the data. In general speaking, this mechanism

probably consists of at least one of the following items: the packet buffer manager, the application

program and OS.

The EEE module works well at LPI (Low Power Idle) mode when

1. Link at full-duplex and

2. Auto-negotiation is enabled in both local and remote PHYs and

3. 100Mbps and

4. EEE ability is supported in both local & remote PHYs and

5. EEE_EN (MMD register 7.60[1]) is enabled for EEE function via default value.

In general applications, the energy-saving mechanism is activated by the real-time OS or the higher

layer hardware. When the OS or higher layer hardware knows that it’s the time to force the unused

function to enter standby mode or sleeping mode, it can force the MAC to send IEEE 802.3az compliant

command to set IP101G to “low power idle” mode. Once entering the “low power idle” mode, IP101G will

stay at a low power consumption level without losing the link capability. After awaken, it can generate a

INTR signal, hardware pin from IP101G, to notify the CPU or external circuitry.

IP101G supports not only EEE ability at 100Mbps but also smaller transmit amplitude requirement at

10Mbps. That complies with 10Base-T PHY interoperability over 100 meters of Category 5 or better

cable types.

5.3.3 Force power down

IP101G can be power-down by 2 methods. These 2 methods are as follows.

Power Down in bit 11 of Register 0: Enable this bit will disconnect the power to IP101G and also

internal clock, but MDC and MDIO are still activated.

Analog off in bit 0 of Register 16: Enable this bit will put IP101G in analog off state. This will power

down all analog functions but internal 25MHz operating clock is active, and MDC and MDIO are also

activated.

5.3.4 WOL+ operation mode

The huge amount of legacy Ethernet devices will make an Ethernet device which supports 802.3az

lost his energy saving capability, because they can not talk to each other for settling down the idle

schedule. IP101G to be a full-range-green Ethernet PHY, not only consumes very low power and with

802.3az capability, but also supports a WOL+ function for solving this issue.

IP101G supports WOL+ either master mode or slave mode. In master mode, the WOL+ function

will be active if all ports are in idle state has been continuously held for a period time. This period time

can be configured by WOL+ timer register (Page4 Reg16[7:6]).

IP101G-DS-R01 数据表(PDF) 48 Page - List of Unclassifed Manufacturers

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