IP101G-DS-R01 datasheet(20/65 Pages) ETC

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IP101G

Data Sheet

Page

Description

Default

Note

PHY WOL+ Status Register

0x0000

RX Counter Interrupt Control/Status Register

0x0000

R/W = Read/Write, SC = Self-Clearing, RO = Read Only, LL = Latching Low, LH = Latching High

(TP): for twisted pair operation. (FX): for fiber operation.

(e-fuse): only available for IP101G (dice).

4.1 Register Page mode Control Register

MII register 20

PHY

MII

ROM

R/W

Description

Default

Page Control Register

20[4:0]

R/W Reg16~31_Page_Sel[4:0]

0x10

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

4.2 MII Registers

Bit

Name

Description/Usage

Default value

(h): 3100

Reset

When set, this action will bring both status and control registers

of the PHY to default state. This bit is self-clearing.

1 = Software reset

0 = Normal operation

0, RW/SC

Loopback

This bit enables loopback of transmit data to the receive data

path, i.e., TXD to RXD.

1 = enable loopback

0 = normal operation

0, RW

Speed Selection

This bit sets the speed of transmission.

1 = 100Mbps

0 = 10Mbps

After completing auto-negotiation, this bit will reflect the speed

status.(1: 100Mbps, 0: 10Mbps)

1, RW

Auto-

Negotiation

Enable

This bit determines the auto-negotiation function.

1 = enable auto-negotiation; bits 13 and 8 will be ignored.

0 = disable auto-negotiation; bits 13 and 8 will determine the link

speed and the data transfer mode, under this condition.

1, RW (TP)

0, RO (FX)

Power Down

This bit will turn down the power of the PHY chip and the internal

crystal oscillator circuit if this bit is enabled. The MDC and MDIO

are still activated for accessing to the MAC.

1 = power down

0 = normal operation

0, RW

Isolate

1=electrically Isolate PHY from MII but not isolate MDC and

MDIO

0,RW

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January 14, 2014

IP101G-DS-R01

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