IP101G-DS-R01 datasheet(42/65 Pages) ETC

42 / 65 page

IP101G

Data Sheet

42/65

January 14, 2014

IP101G-DS-R01

After MAC passes data to PHY via 4 bits nibbles, the data are serialized in the parallel to serial converter.

The converter outputs NRZI coded data which the data are then mapped to Manchester code within the

Manchester Encoder. Before transmitting to the physical medium, the Manchester coded data are

shaped by D/A converter to fit the physical medium.

10Mbps Receive:

RXI

Squelch

Clock Recovery

Manchester/NRZ Decoder

Serial to Parallel

RXD

The squelch block determines valid data from both AC timing and DC amplitude measurement. When a

valid data is present in the medium, squelch block will generate a signal to indicate the data has received.

The data receive are coded in Manchester form, and are decoded in the Manchester to NRZ Decoder.

Then the data are mapped to 4 bits nibbles and transmitted onto MAC interface.

100Mbps TX Transmit:

TXD

4B/5B Encoder

Scrambler

Mux

Parallel to Serial

NRZI/MLT-3 Encoder

D/A & line

driver

TXO

The major differences between 10Mbps transmission and 100Mbps transmission are that 100Mbps

transmission requires to be coded from 4-bit wide nibbles to 5 bits wide data coding, and after that the

data are scrambled through scrambler to reduce the radiated energy generated by the 4B/5B

conversion.

Then the data is converted into NRZI form and again from NRZI coded form into MLT-3 form. The MLT-3

data form is fed into D/A converter and shaped to fit the physical medium transmission.

100Mbps RX Receive:

RXI

DSP

MLT-3/NRZI Decoder

Clock Recovery

Serial to Parallel

Descrambler

4B/5B

Decoder

RXD

The received data first go through DSP engines which includes adaptive equalizer and base-line wander

correction mechanism. The adaptive equalizer will compensate the loss of signals during the

transmission, while base-line wander monitors and corrects the equalization process. If a valid data is

detected then the data are parallelized in Serial to Parallel block, which it converts NRZI coded data form

back to scrambled data. The scrambled data are descrambled and converted back to 4 bits–wide format

data and then feed into MAC.

5.1.2 MII and Management Control Interface

Media Independent Interface (MII) is described in clause 22 in the IEEE 802.3u standard. The main

function of this interface is to provide a communication path between PHY and MAC/Repeater. It can

operate either in 10Mbps or 100Mbps environment, and operate at 2.5MHz frequency for 10Mbps clock

data rate or 25MHz frequency for 100Mbps data rate transmission. MII consists of 4 bit wide data path for

both transmit and receive. The transmission pins consists of TXD[3:0], TX_EN and TXC, and at receiving

MII pins have RXD[3:0], RXER, RX_DV and RXC. The Management control pins include MDC and

MDIO. MDC, Management Data Clock, provides management data clock period can be to 300ns as a

reference for MDIO, Management Data Input/Output. CRS, Carrier Sense, is used for signaling data

transmission is in process while COL, Collision, is used for signaling the occurrence of collision during

transmission.

Transmitting a packet, MAC will first assert TX_EN and convert the information into 4 bits wide data and

then pass the data to IP101G. IP101G will sample the data according to TX_CLK until TX_EN is low.

While receiving a packet, IP101G asserts RX_DV high when data present in the medium through

RXD[3:0] bus lines. IP101G samples received data according to RX_CLK until the medium is back to idle

state.

The MDI transmitter of IP101G can enter low power idle (LPI) state via TX_ER, TXD[3:0] and TX_EN as

the following behavior.

IP101G-DS-R01 数据表(PDF) 42 Page - List of Unclassifed Manufacturers

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