IP101G-DS-R01 datasheet(46/65 Pages) ETC

46 / 65 page

IP101G

Data Sheet

Once the negotiation has completed with the other party, IP101G will configure itself to the desired

connection mode, i.e., 10/100Mbps or Half/Full duplex modes. If there is no detection of link pulses

within 1200~1500ms, IP101G will enter Link Fail State and restart auto-negotiation procedure.

The auto-negotiation information is stored in the IP101G’s MII registers. These registers can be modified

and monitor the IP101G’s Auto-Negotiation status. The reset auto-negotiation in register 0 of MII

registers can be set at any time to restart auto-negotiation.

The flow control ability is also included in the IP101G chip. If MAC supports flow control condition, then

flow control will be enabled by setting bit 10 (Pause) of the Register 4.

We can determine the link speed and EEE ability from IP101G’s MII registers. There is an example as

following figure.

Figure 11 IP101G link speed and EEE ability programming guide

5.1.6 Auto-MDIX function

IP101G will keep sensing incoming signal in MDI RX pair, if no incoming signal is detected, IP101G will

switch TX and RX pairs automatically trying to establish connection. IP101G supports this function both

in Auto-Negotiation mode and force mode.

5.2 PHY Address Configuration

IP101GR/IP101GRI PHY Address can be configured to 5’d0, 5’d1 or response any one PHY address

from 5’d2 to 5’d31. IP101G/IP101GA PHY Address can be configured to 5’d0, 5’d1,…, 5’d7 or response

any one PHY address from 5’d8 to 5’d31. This PHY Address configuration is the following table.

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January 14, 2014

IP101G-DS-R01

IP101G-DS-R01 数据表(PDF) 46 Page - List of Unclassifed Manufacturers