IP101G-DS-R01 datasheet(47/65 Pages) ETC

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IP101G

Data Sheet

Table 4 PHY Address Configuration

Pin name

Package

LED3/PHY_AD3 LED2/PHY_AD2 LED1/PHY_AD1 LED0/PHY_AD0

PHY Address

setting

5’d0

5’d1

32 pin

5’d2 ~ 5’d31

5’d0

5’d1

5’d2

5’d3

5’d4

5’d5

5’d6

5’d7

48 pin

5’d8 ~ 5’d31

Note: “X” indicate don’t care (either 1 or 0). Do not let these PHY address pins floating for the latched-in

settings after the power is ready.

LED pins also include the information of PHY address. The PHY address can be modified by changing

the LED circuitry. The modification can be arranged as follows.

Figure 12 PHY Address Configuration

The left diagram will enable the specific PHY address to 1, if it is connected to VDD33. The diagram on

the right shows the configuration for setting PHY address to 0, when the circuit is connected to ground.

By setting either one of the bits according to the diagram will allow one to modify PHY addresses from

PHY_AD0 to PHY_AD3.

5.3 Power Management Tool

IP101G provides rich power management tool to save the power consumption. They are

APS, auto power saving while Link-off

802.3az, protocol based power saving

PWD, force power down

WOL+, light traffic power saving

5.3.1 Auto Power Saving Mode

APS mode while link is down, MDC and MDIO are kept activated. IP101G will send NLP every

256ms or (256*N)ms during APS sleeping mode, and the symbol N is an integer such as 2,3,4… random

seed for power saving.

47/65

January 14, 2014

IP101G-DS-R01

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