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IP101G-DS-R01 数据表(PDF) 37 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 37 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
37/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
MII page4 register16
page
MII
ROM R/W
Description
Default
16[5]
R/W
(SC)
WOL_PLUS_MANUAL_SET
WOL+ Manual Set.
CPU/MAC can set high to sleep mode or wake up in slave
mode.
1=Manual set sleep/wake in WOL+ slave mode.
0=Disable.
0
16[4:0]
RO
Reserved
0x00
MII page5 register16
page
MII
ROM R/W
Description
Default
PHY WOL+ MAC Address Register
5
16[15:0]
R/W WOL_PLUS_MAC_ADDR
WOL+ MAC address table.
Continuously write/read this register 3 times to set/obtain
WOL+ Magic packet MAC address.
The sequence of MAC address is [31~16], [47~32] then [15~0].
0x0000
MII page17 register17
page
MII
ROM R/W
Description
Default
PHY WOL+ Status Register
17
17[15]
R/W WOL_PLUS_INTR_PIN_DIS
WOL+ interrupt pin disable.
Interrupt pin INTR is served to WOL+ event only, when this bit
set to 0 and not only enable WOL_PLUS_EN (Page4
Reg16[15]=1) but also INTR pin used (Page16 Reg17[15]=1).
INTR pin
used
(P16R17
[15])
WOL_PL
US_EN
(P4R16[
15])
WOL_PLUS_
INT_PIN_DI
S
(P17R17[15])
INTR pin function
0
X
X
Disable
1
0
0
1
X
1
Not including WOL+
interrupt status
1
1
0
Only for WOL+ interrupt
status
0
17
17[14:4]
RO
Reserved
0x000
17
17[3]
RO
(SC)
WOL_PLUS_INTR_STATUS
WOL+ interrupt status.
1=Interrupt event.
0=Normal (no any interrupt event).
0
17
17[2]
RO
WOL_PLUS_SLEEPING
WOL+ sleeping status.
This bit is a real-time status in WOL+ sleep mode.
1=IP101G is in WOL+ sleeping mode.
0



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