IP101G-DS-R01 datasheet(41/65 Pages) ETC

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IP101G

Data Sheet

41/65

January 14, 2014

IP101G-DS-R01

Function Description

IP101G 10/100Mbps Ethernet PHY Transceiver integrates 100 Base-TX and 10 Base-T modules into a

single chip. IP101G acts as an interface between physical signaling and Media Access Controller (MAC).

IP101G has several major functions:

1. PCS layer (Physical Coding Sub-Layer): This function contains transmit, receive and carrier sense

functional circuitries.

2. Management interface: Media Independent Interface (MII) or Reduced Management Interface

(RMII) registers contains information for communication with other MAC.

3. Auto-Negotiation: Communication conditions between 2 PHY transceivers. IP101G advertise its

own ability and also detects corresponding operational mode from the other party, eventually both

sides will come to an agreement for their optimized transmission mode.

5.1 Major Functional Block Description

The functional blocks diagram is referred to Figure 1:

4B/5B encoder:

100 Base-X transmissions require converting 4-bit nibble data into 5-bit wide data

code-word format. Transmitting data is packaged by J/K codes at the start of packet and by T/R

codes at the end of packet in the 4B/5B block. When transmit error has occurred during a

transmitting process, the H error code will be sent. The idle code is sent between two packets.

b. 4B/5B Decoder:

The decoder performs the 5B/4B decoding from the received code-groups. The 5

bits (5B) data is decoded into four bits nibble data. The decoded 4 bit (4B) data is then forwarded

through MII to the repeater, switch or MAC device. The SSD is then converted into 4B 5 nibbles and

the ESD and IDLE Codes are replaced by 4B 0 nibbles data. The decoded data is driven onto the

corresponding MII port or shared MII port. Receiving an invalid code group will cause PHY to assert

the MII RXER signal.

Scrambler/Descrambler:

Repetitive patterns exist in 4B/5B encoded data which result in large RF

spectrum peaks and keep the system from being approved by regulatory agencies. The peak in the

radiated signal is reduced significantly by scrambling the transmitted signal. Scrambler adds a

random generator to the data signal output. The resulting signal is with fewer repetitive data patterns.

The scrambled data stream is descrambled at the receiver by adding another random generator to

the output. The receiver’s random generator has the same function as the transmitter’s random

generator. Scrambler operation is dictated by the 100Base-TX and TP_FDDI standards.

d. NRZI/MLT-3(Manchester) Encoder and Decoder:

100Base-TX Transmission requires encoding

the data into NRZ format and again converted into MLT-3 signal, while 10 Base-T will convert into

Manchester form after NRZ coding. This helps to remove the high frequency noise generated by the

twisted pair cables. At receiving end, the coding is reversed from MLT-3 (Manchester) signal back to

NRZ format.

e. Clock Recovery: The receiver circuit recovers data from the input stream by regenerating clocking

information embedded in the serial stream. The clock recovery block extracts the RXCLK from the

transition of received

DSP Engine:

This block includes Adaptive equalizer and Base Line Wander correction function.

5.1.1 Transmission Description

10Mbps Transmit flow path:

TXD

Parallel to Serial

NRZI/Manchester Encoder

D/A & line driver

TXO

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