IP101G-DS-R01 datasheet(6/65 Pages) ETC

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IP101G

Data Sheet

6/65

January 14, 2014

IP101G-DS-R01

Revision History

Revision #

Change Description

IP101G-DS-R01

Initial release.

IP101G-DS-R01-20120726 1) Add more description of Register RX2TX_LPBK P1R23[13] for Rx to Tx

loopback test.

2) Add more description on Fiber Mode Setting and latched-in pin signals

on AC Timing.

3) Add IP101AH into the table of features comparison.

IP101G-DS-R01-20120808 1) Correct the I/O type of IP101GA pin description to O(Ouput) for pin24

RXER.

2) Change the pin name from DVDD33_IO to VDDIO.

IP101G-DS-R01-20120821 1) Change the default value of register P16R27 from 0x0022 to 0x0012.

2) Remove I/O Slew Rate Control Register.

3) Change the register location RMII_WITH_ER from P16R29[0] to

P16R29[7].

IP101G-DS-R01-20120927 1) Add more description of low power idle (LPI) state in MII and RMII

modes.

2) Correct the typo of Physical Dimensions.

IP101G-DS-R01-20121101 Change the LED blink timing from “On 80ms -> Off (20~40)ms” to “On 26ms

-> Off 78ms”.

IP101G-DS-R01-20121113 Add more function description to support Jumbo Frame.

IP101G-DS-R01-20121127 Change the LED mode function as same as IP101A.

IP101G-DS-R01-20121224 Add the notice that does not let these PHY address pins floating for the

latched-in settings after the power is ready.

IP101G-DS-R01-20130206 Change the AC timing Tclk_MII_rdy in Table 14 from 10ms Min. to 10ms Max.

IP101G-DS-R01-20130312 1) Add more Min. and Max value on the AC Timing table.

2) Add thermal data on the Table 20.

IP101G-DS-R01-20130507 Add LED Pin Driving Control Register.

IP101G-DS-R01-20130621 Add IP101GRI 2.5V I/O power supply.

IP101G-DS-R01-20130712 Modify WOL+ programming guide.

IP101G-DS-R01-20130830 Modify Magic packet MAC_Address description.

IP101G-DS-R01-20130905 Modify LED Control Register.

IP101G-DS-R01-20130927 Modify MDC clock period can be to 300ns.

IP101G-DS-R01-20131110 Add the symbol "Bottom view" and "Top view" in Physical Dimensions.

IP101G-DS-R01-20131115 Add Equivalent Series Resistance and Drive Level in Crystal Specifications.

IP101G-DS-R01-20140114 1) Make more clear between 100Mbps (25M nibbles/s) and 25M

code-groups/s in Figure 1 Flow chart of IP101G.

2) Change all symbols from “VQFN” to “QFN”.

3) Add the key word “Fiber” in Table 11 I/O Electrical Characteristics.

4) Add register PHY_ADDRESS in Page16 Reg29 bit[12:8].

Disclaimer

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