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IP101G-DS-R01 数据表(PDF) 28 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 28 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
28/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
MII page16 register29
page
MII
ROM R/W
Description
Default
Digital I/O Specific Control Register
29[15:13]
RO Reserved
3’b000
29[12:8]
R/W PHY_ADDRESS
The initial PHY address [4:0] is determined via pin setting in
Table 4 PHY Address Configuration. If user changes the
register of PHY_ADDRESS, the SMI(MDC/MDIO) read/write
command should change “PHY address” value at the same
time.
Pin
setting
29[7]
R/W RMII_WITH_ER
1: enable TXER/RXER function in RMII mode.
0: disable TXER/RXER function in RMII mode.
1
29[6:3]
R/W Reserved
4’b0000
29[2]
R/W SEL_INTR32
The multiplex function is for 32pin package at pin21
RXER/INTR_32.
1: INTR function
0: RXER function
0
16
29[1:0]
R/W Reserved
2’b10
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
MII page16 register30
page
MII
ROM R/W
Description
Default
PHY MDI/MDIX Control and Specific Status Register
30[15:9]
RO Reserved
0
30[8]
RO LINK_UP
To indicate the link status is OK or FAIL
0
30[7:4]
RO Reserved
0
30[3]
R/W FORCE_MDIX
Set high to force the MDIX channel to be selected.
1: Force the MDIX channel to be selected.
0: MDI channel is selected when auto-MDIX is turned off.
When IP101G operates in Force 10Mbps mode or APS mode,
this bit is not able to write.
0
16
30[2:0]
RO OP_MODE_IND
Operation Mode Idicator
000= Link off
001= 10M Half
010= 100M Half
011= Reserved
100= Reserved
101= 10M Full
110= 100M Full
111= Reserved
3’b000



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