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IP101G-DS-R01 数据表(PDF) 18 Page - List of Unclassifed Manufacturers |
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IP101G-DS-R01 数据表(HTML) 18 Page - List of Unclassifed Manufacturers |
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18 / 65 page ![]() IP101G Data Sheet 18/65 January 14, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 IP101GR/GRI Pin no. Label Type Reset Description State 3 X2 O O 25MHz Crystal Output: Connects to crystal to provide the 25MHz output. It must be left open when X1 is driven with an external 25MHz oscillator. 2 X1 I I 25MHz Crystal Input: Connects to crystal to provide the 25MHz crystal input. If a 25MHz oscillator is used, connect X1 to the oscillator’s output. If a 50MHz clock is applied to pin10 TXCLK/50M_CLKI, X1 must be connected to GND. 32 RESET_N I I (PU) RESET_N: Enable a low status signal will reset the chip. For a complete reset function. 25MHz clock (x1) must be active for a minimum of 10 clock cycles before the rising edge of RESET_N. Chip will be able to operate after 2.5ms delay of the rising edge of RESET_N. The 2.5ms extension is to ensure the stability of system power. 25 ISET I I Bandgap Circuit Resistor: This pin should be connected to GND via a 6.19KΩ (1%) resistor to define the standard current of the internal circuit. 11 LED0/PHY_AD0 O/LI Hi-Z LED 0 and PHY Address [0] LED 0 LED mode 1 2 LED0 Link Link /ACT(blinking) 12 LED3/PHY_AD3 O/LI (PD) Hi-Z LED 3 and PHY Address [3] LED3 LED mode 1 2 LED3 100M Link /ACT 100M Link 24 TEST_ON I (PD) I (PD) Test Enable: Set this pin to high to enable Test mode. For normal operation, this pin doesn’t need to be connected. Power and Ground 28 REGOUT P P Regulator Power Output: This is a regulator power output. A 10uF and 0.1uF should be connected to this pin to filter the power noise. 13 VDDIO P P Digital Power input: IP101GR/GRI: Either 3.3V or 2.5V for I/O power supply. 31 AVDD33 P P 3.3V Analog power input: This is a 3.3V power supply for analog circuitry, and it should be decoupled carefully. Bottom PAD GND P P Ground . |
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