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IP101G-DS-R01 数据表(PDF) 12 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 12 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
12/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
3
Pin description
Type
Description
Type
Description
LI
Latched Input in power up or reset
PD
Internal Pull-Down 104KΩ
I/O
Bi-directional input and output
PU
Internal Pull-Up 222KΩ
I
Input
Hi-Z
High impedance
O
Output
P
Power
OD
Open Drain
3.1 IP101GA pin description
IP101GA
Pin no.
Label
Type
Reset
State
Description
Serial Management Interface Pins
25
MDC
I
Hi-Z Management Data Interface Clock: This pin provides a
clock reference to MDIO. The clock period can be to
300ns.
26
MDIO
I/O
(PU)
I
(PU)
Management
Data
interface
Input/Output:
The
function of this pin is to transfer management information
between PHY and MAC.
MII/RMII Pins
2
TXEN
I
(PD)
I
(PD)
Transmit Enable or Signal Detect.
43
TXER/FXSD
I
(PD)
I
(PD)
Transmit Error or FXSD:
This is a dual-function pin which is determined by the
media type selection. If RXDV/CRS_DV/FX_HEN is
latched as “0 (default)” upon reset, the TP interface is
selected and its function as TXER. If the fiber interface is
selected, this pin’s function as FXSD.
FXSD:
0: Fiber link down; 1: Fiber link up
Transmit Enable:
TXEN
TXER
Description
1
1
Transmission error
propagation.
0
1
Combine TXD[3:0] that equal
to 0001 for request PHY to
enter LPI mode.
1
0
0
0
Normal operation
This pin TXER must be either floating or connecting to
GND in RMII mode.
7
TXCLK/50M_CLKI
I/O
Hi-Z Transmit Clock output or 50M clock input:
In MII mode, this pin provides a continuous 25MHz clock
at 100Base-TX and 2.5MHz at 10Base-T.
In RMII mode, a 50Mhz clock should input to this pin for
the timing reference of the internal circuit.
3,4,5,6 TXD[3:0]
I
Hi-Z Transmit Data Input:



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