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IP101G-DS-R01 数据表(PDF) 34 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 34 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
34/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
4.5 RX Counter Register
MII page1 register17
page
MII
ROM R/W
Description
Default
RX Counter Control Register
1
17[13]
R/W RX Counter Enable
0= RX Counter Disable
1= RX Counter Enable for CRC_ERR_CNT(P1R18[15:0]),
PKT_STS_CNT(P2R18[15:0]) and
SYMB_ERR_CNT(P11R18[15:0]).
0
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
MII page1 register18
page
MII
ROM R/W
Description
Default
RX CRC Error Counter Register
1
18[15:0]
RO CRC_ERR_CNT
RX CRC error counter
0x0000
MII page2 register18
page
MII
ROM R/W
Description
Default
RX Packet Counter Register
2
18[15:0]
RO PKT_STS_CNT
RX packet status counter (include CRC good and error packet)
0x0000
MII page8 register17
page
MII
ROM R/W
Description
Default
RX Counter Control Register
17[15]
R/W RXERR_CNT_RDCLR_EN
Set 1 to clear RX error counter after reading
0
17[14]
R/W RXERR_CNT_REPEAT
This bit is set to 0 when RXERR_INTR_EN = 1
1
17[13:12]
R/W RXERR_CNTDOWN_SEL
Select the RX error countdown value
2’b00: 1
2’b01: 255
2’b10: 1023
2’b11: 65535
2’b11
8
17[11:0]
RO Reserved
0x000
MII page11 register18
page
MII
ROM R/W
Description
Default
UTP PHY Interrupt Control/Status Register



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