IP101G-DS-R01 datasheet(45/65 Pages) ETC

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IP101G

Data Sheet

5.1.4 Flexible Clock Source

While set COL/RMII pin to logic 1, 50MHz reference clock will be provided by IP101G in RMII mode. For

this configuration, RMII reference clock output for IP101G is from RXCLK/50M_CLKO. Clock skew could

be eliminated by adding an external buffer and placing equal trace lengths between buffer outputs and

each chip.

The flexible clock source is list as the following table.

Table 3 Flexible Clock Source Setting

Pin name

COL/RMII

Mode

Clock Source

Function

Crystal 25MHz Provides a crystal 25MHz into pin X1 and X2.

Clock 25MHz

Provides a clock source 25MHz into pin X1.

RMII

Clock 50MHz

Provides a clock source 50MHz into pin TXCLK/50M_CLKI and

connect pin X1 to GND or AGND33.

Crystal 25MHz Provides a crystal 25MHz into pin X1 and X2.

MII

Clock 25MHz

Provides a clock source 25MHz into pin X1.

Figure 10 IP101GR need add a buffer if RXCLK/50M_CLK push over two device

5.1.5 Auto-Negotiation and Related Information

IP101G supports clause 28 in the IEEE 802.3u standard. IP101G can be operated either in

10Mbps/100Mbps or half/full duplex transmission mode. IP101G also supports flow control mechanism

to prevent any collision in the network. If the other end does not support Auto-Negotiation function,

IP101G will link at half duplex mode and enter parallel detection.

At beginning of auto-negotiation, IP101G will advertise its own ability by sending FLP waveform out to

the other end and also listening signals from the other end. IP101G will place itself into correct

connection speed depends on the received signals. If NLP signal is replied from the other end, IP101G

will enter 10Mbps, while active idle pulses (unique 100Mbps pattern) IP101G will go to 100Mbps mode

instead.

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January 14, 2014

IP101G-DS-R01

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