IP101G-DS-R01 datasheet(31/65 Pages) ETC

31 / 65 page

IP101G

Data Sheet

31/65

January 14, 2014

IP101G-DS-R01

4.4 MMD Data Register

MMD register 3.0

Page

MII

ROM

R/W

Description

Default

PCS Control 1 Register

3.0[15:11]

Reserved

Ignore when read

3.0.10

R/W

Clock stop enable

1 = IP101G may stop xMII Rx clock during LPI

0 = Clock not stoppable

3.0[9:0]

Reserved

Ignore when read

MMD register 3.1

page

MII

ROM

R/W

Description

Default

PCS Status 1 Register

3.1[15:12]

Reserved

Ignore when read

3.1.11

RO/LH Tx LPI received

1 = Tx PCS has received LPI

0 = LPI not received

3.1.10

RO/LH Rx LPI received

1 = Rx PCS has received LPI

0 = LPI not received

3.1.9

Tx LPI indication

1 = Tx PCS is currently receiving LPI

0 = PCS is not currently receiving LPI

3.1.8

Rx LPI indication

1 = Rx PCS is currently receiving LPI

0 = PCS is not currently receiving LPI

3.1.7

Reserved

Ignore on read

3.1.6

Clock stop capable

1 = The MAC may stop the clock during LPI

0 = Clock not stoppable

3.1[5:0]

Reserved

Ignore when read

MMD register 3.20

page

MII

ROM

R/W

Description

Default

EEE Capability Register

3.20[15:7]

RO Reserved

Ignore when read

IP101G-DS-R01 数据表(PDF) 31 Page - List of Unclassifed Manufacturers

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IP101G-DS-R01 数据表(PDF) 31 Page - List of Unclassifed Manufacturers

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