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IP101G-DS-R01 数据表(PDF) 36 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 36 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
36/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
MII page4 register16
page
MII
ROM R/W
Description
Default
16[15]
R/W WOL_PLUS_EN
WOL+ enable function.
Set high to enable WOL+ function.
1=Enable
0=Disable
0
16[14]
R/W WOL_PLUS_MASTER
WOL+ master mode setting.
This bit is used to select WOL+ either master mode or slave
mode.
1=WOL+ Master mode
0=WOL+ Slave mode
1
16[13]
R/W INTR_ACT_HIGH
Interrupt active high.
This bit is used to select the active level either high or low of
interrupt pin.
1=Pin "INTR" is set to output type and active high.
0=Pin "INTR" is set to open drain type and active low.
0
16[12]
R/W Reserved
1
16[11]
R/W SENSE_MAGIC_PKT
Sense Magic Packet.
Set high to enable WOL+ interrupt when magic packet is
receiving.
1=Enable
0=Disable
1
16[10]
R/W SENSE_ANY_PKT
Sense Any Packet.
Set high to enable WOL+ interrupt when any good CRC packet
is receiving.
1=Enable
0=Disable
1
16[9]
R/W SENSE_DUT
Sense DUT.
Set high to enable wake up event detection (magic packet, any
packet) of corresponding port.
1=Enable
0=Disable
1
16[8]
R/W WOL_PLUS_DNSPD_EN
WOL+ Down Speed Enable.
Set high to enable WOL+ down speed function
1=Enable
0=Disable
1
4
16[7:6]
R/W WOL_PLUS_TIMER_SEL
WOL+ Timer Select,
2’b00 = 30 seconds.
2’b01 = 3 minutes.
2’b10 = Reserved for internal test used.
2’b11 = 10 minutes.
2’b01



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