IP101G

Data Sheet

4/65

January 14, 2014

Copyright © 2011, IC Plus Corp.

IP101G-DS-R01

List of Figures

Figure 1 Flow chart of IP101G ..................................................................................................................8

Figure 2 IP101GA 48 Pin Top view Diagram .............................................................................................9

Figure 3 IP101GR/GRI 32 Pin Top view Diagram ...................................................................................10

Figure 4 IP101G dice pad information Top view...................................................................................... 11

Figure 5 LPI transition .............................................................................................................................43

Figure 6 IP101G/GA/GR/GRI MII Mode with LPI transition Block Diagram............................................43

Figure 7 IP101G/GA/GR/GRI MII Mode without LPI transition Block Diagram.......................................43

Figure 8 IP101G RMII Mode with internal clock Block Diagram .............................................................44

Figure 9 IP101G RMII Mode with external clock Block Diagram ............................................................44

Figure 10 IP101GR need add a buffer if RXCLK/50M_CLK push over two device ................................45

Figure 11 IP101G link speed and EEE ability programming guide .........................................................46

Figure 12 PHY Address Configuration ....................................................................................................47

Figure 13 Magic Packet Format ..............................................................................................................49

Figure 14 Sleep or wake up automatically programming guide ..............................................................50

Figure 15 MAC control sleep or wake up programming guide................................................................51

Figure 16 MDC/MDIO Format .................................................................................................................53

Figure 17 IP101G Fiber Mode Setting.....................................................................................................54

Figure 18 Reset, Pin Latched-In, Clock and Power Source Timing Requirements.................................58

Figure 19 MII Transmit Timing Requirements .........................................................................................59

Figure 20 MII Receive Timing Specifications ..........................................................................................59

Figure 21 RMII Transmit Timing Requirements.......................................................................................60

Figure 22 RMII Receive Timing Specifications........................................................................................60

Figure 23 SMI Timing Requirements.......................................................................................................61

Figure 24 48-PIN LQFP Dimension.........................................................................................................63

Figure 25 32-PIN QFN Dimension ..........................................................................................................64