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IP101G-DS-R01 数据表(PDF) 26 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 26 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
26/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
MII page16 register16
page
MII
ROM R/W
Description
Default
16[8]
R/W FEF_DISABLE
To enable or disable the functionality of Far-End Fault
Mode
Enable
Disable
100Base-TX
1
0
0
16[7]
R/W NWAY_PSAVE_DIS
Set high to disable the power saving during auto-negotiation
0
16[6]
RO Reserved
0
16[5]
R/W BYPASS_DSP_RESET
Set high to bypass the reset DSP mechanism in PCS sub-layer
0
16[4:3]
RO Reserved
2’b00
16[2]
R/W REPEATER_MODE
Set high to put IP101G into repeater mode
0
16[1]
R/W Reserved
1
16[0]
R/W ANALOG_OFF
Set high to power down analog transceiver
0
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
MII page16 register17
page
MII
ROM R/W
Description
Default
Interrupt Status Register
17[15]
R/W INTR pin used
Interrupt pin used.
Set high to enable INTR or INTR_32 as an interrupt pin. Pin
INTR or INTR_32 will be high impedance if this bit is set low.
0
17[14:12]
RO Reserved
3’b000
17[11]
R/W All Mask
When this bit is set high, flags to be raised on bit 6, 2, 1 and 0
will not cause an interrupt.
1
17[10]
R/W Speed Mask
When this bit is set high, changes in speed mode will not cause
an interrupt.
1
17[9]
R/W Duplex Mask
When this bit is set high, changes in duplex mode will not
cause an interrupt.
1
17[8]
R/W Link Mask
When this bit is set high, changes in link status will not cause
an interrupt.
1
17[7:4]
RO Reserved
0x0
17[3]
RO
(SC)
INTR Status
Flag to indicate interrupt status
0
16
17[2]
RO
(SC)
Speed Change
Flag to indicate speed change interrupt
0



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